Very high voltage isolation on silicon or other semiconductor material chips requires a box of isolation material surrounding the active region on the semiconductor chip. Typically vertical isolation is achieved by making use of a Silicon on Insulator (SOI) process with a SOI underlying layer defining the lower boundary of the isolated active region, and an overlying layer of dielectric material forming the upper boundary of the active region. Lateral isolation is, in turn, achieved by etching a trench around the active region and filling the trench with dielectric material such as oxide, an oxide, nitride stack, an oxide, nitride, polysilicon stack, or other dielectric material. By virtue of its box-like configuration this type of isolation is commonly referred to as box isolation. It will be appreciated that the isolation thickness has to be increased as the voltage levels increase.
A problem encountered in the past when dealing with very high lateral voltage isolation is that as the film thickness of the dielectric increases, film stresses in the dielectric film become ever more apparent. At a trench width of about 6 um, the film thickness along each wall of the trench is about 3 um, and leads to excessive film stress, thus essentially limiting the maximum voltage that can be isolated in a lateral direction. In order to isolate to a level of 1000V for example, a 20 um wide trench filled with dielectric is required, which is not feasible using the above-described technique.
One prior art solution has been to form two or more concentric trenches that are each sufficiently narrow so as not to suffer from film stress problems. However, due to the resultant silicon bands or islands that are formed between the filled trenches a charging effect occurs of the intermediate silicon, which results in a voltage drift of the floating nodes defined by the trenches. This is best illustrated by the sectional view of FIG. 1, which shows an active area 100 located on top of a SOI layer 102. A first dielectric filled trench 104 is formed around the active region and a second dielectric filled trench 106 is formed concentrically around the first trench 104. FIG. 1 shows an additional dielectric filled trench 110. Over time the high lateral voltage (in this case 1000V) applied at location 120 charges the silicon between trenches 104 and 110, which can cause anomalous effects such as sidewall inversion, parasitic substrate currents and drift of adjacent devices
The present invention seeks to provide a new approach for high lateral voltage isolation that does not suffer from the above mentioned limitations.